Clock dividing frequency is an operation that reduces the constant system clock frequency by an integral multiple. In a large-scale circuit with a plurality of different modules (e.g., a power management IC having a plurality of switching regulators), all channels in the integrated circuit may share the same system clock such that each channel is synchronized, in order to optimize noise performance and save chip space. Due to characteristics of each module/circuit, the local clock frequency may be less than the system clock frequency in order to provide protection. In an example switching converter with a buck topology, the local clock frequency may be reduced in order to protect the power stage circuit. Although the system clock signal can be digitally divided, it can be difficult to change the clock frequency smoothly and proportionally according to the voltage difference in such cases.